Senior Synthesis and STA Engineer / Lead

Texas Instruments

Bengaluru, Karnataka, India Design Engineering
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Senior STA and Synthesis Engineer / STA Lead - Texas Instruments

About the Role: Join Texas Instruments' Connectivity engineering team as a Senior STA and Synthesis Engineer / STA Lead, where you'll play a critical role in delivering high-performance wireless connectivity solutions that power next-generation IoT, automotive, and industrial applications.

What You'll Do: Drive timing closure and synthesis optimization for advanced connectivity SoCs, ensuring our wireless solutions meet stringent performance, power, and area requirements across diverse market applications.

Technical Focus:

Multi-Technology Expertise: Work on synthesis and timing analysis across various wireless connectivity standards and protocols

Full Flow Ownership: Drive synthesis, timing analysis, and optimization from RTL to layout handoff

Performance Leadership: Ensure timing closure for complex mixed-signal connectivity designs

Key Responsibilities:

• Perform static timing analysis and synthesis for connectivity SoCs

• Collaborate with design teams to optimize RTL for timing, power, and area

• Write SDC constraints across functional and DFT modes and validate the constraints through industry standard constraints checker tools

• Drive timing closure through physical design flow coordination

• Develop and maintain synthesis and STA methodologies and scripts

Growth Opportunities:

• Work on both established connectivity platforms and breakthrough wireless technologies

• Contribute to multiple tape-outs annually across different process nodes

• Influence next-generation connectivity architecture decisions

• Mentorship opportunities with junior engineers and cross-functional collaboration

Why This Role:

• Direct impact on TI's wireless connectivity portfolio performance

• Exposure to diverse wireless standards and emerging technologies

• Opportunity to work with state-of-the-art EDA tools and methodologies

• Be part of innovation initiatives including new wireless technologies for TI

Technical Environment:

• Multiple process technology nodes and design rule sets

• Complex mixed-signal connectivity SoC designs

• Automated flow development and optimization

Ready to Drive Connectivity Performance? Join our team and help optimize the wireless technologies that connect our world.

Qualifications


Required Qualifications: Education & Experience:

4-10 years of hands-on experience in synthesis, or static timing analysis

>3 years of experience working on SoC-level designs (>1M gates)

Technical Expertise (Synthesis / STA):

Synthesis & Optimization:

• Proficiency with synthesis tools: Cadence Genus or similar

• Experience with multi-Vt optimization, clock gating, and power optimization techniques

• Knowledge of advanced synthesis constraints and optimization strategies

• Knowledge on Logic equivalence check, CLP

Static Timing Analysis:

• Hands on experience with Cadence Tempus, Synopsys PrimeTime, Complex constraints coding, understanding clocking architecture, DFT constraint modes, IO timing constraints coding for different interfaces like SPI, CAN etc.

• Deep understanding of setup/hold analysis, multi-mode multi-corner (MMMC) timing

• Experience with clock domain crossing (CDC) analysis and timing exceptions

Scripting & Automation:

• Strong programming skills in TCL and Perl

• Experience developing automated flows and regression frameworks

Process & Technology:

• Understanding of process variations, OCV/SoCV, mixed-VT analysis

• Knowledge of low-power design techniques

Design Knowledge:

• Strong understanding of digital design fundamentals and CMOS circuit behavior

• Familiarity with clock tree synthesis (CTS) and clock skew optimization

• Knowledge of DFT (Design for Test) impact on timing and synthesis

Soft Skills & Attributes:

Excellent analytical and problem-solving abilities

Strong written and verbal communication skills for technical documentation and presentations

Self-motivated with ability to work independently and manage multiple projects

Detail-oriented with commitment to quality and accuracy

Adaptability to rapidly evolving technologies and methodologies

Collaborative mindset for working in cross-functional teams

Leadership and mentorship capabilities to lead and build a strong STA team

Skills

SynthesisStatic Timing AnalysisRTL OptimizationCadence GenusCadence TempusPower OptimizationClock GatingMulti-Vt OptimizationCollaborationMentorship